1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices and more particularly to improvements which decrease the displacement of elements formed on a substrate due to photolithographic masking and etching techniques.
2. Description of the Prior Art
In forming a plurality of semiconductor elements on a semiconductor substrate, conventional photoetching techniques give rise not only to the critical problem of displacement of each element but also limit miniaturization of the element patterns.
FIG. 1 shows an integrated circuit consisting of complementary inverter circuits and FIGS. 2A through 2F show the conventional method of manufacturing such an integrated circuit.
Referring to the drawings and particularly to FIG. 2A, an N type silicon substrate 1 is shown as including a P type diffused region 2 in which an N type insulated gate FET is to be formed along with an insulating film 30. The P type region 2 is formed by removing the insulating film 30 selectively to make an opening by any of the well known photoetching techniques and then by diffusing a P type impurity where the film 30 has been removed. In this step, an alignment of the photo mask used during the photoetching is not required.
The substrate 1 is then heated to form another insulating film 31 on the surface thereof. The insulating film 31 is selectively removed by photoetching to make openings 32, 33 and 34. Thereafter an N type impurity is diffused from the openings 32, 33 and 34 to make a source region 3, a drain region 4 and a guard ring or stopper 21 (FIG. 2B). In this step, mask alignment is necessary relative to the P type region 2. However, it is assumed that no relative displacement between the P type region 2 and the source 3, drain 4 or stopper 21 has occured.
The substrate 1 is then heated to form an insulating film 35. The insulating film 35 is selectively removed by photoetching to make openings (not shown) and a P type impurity is diffused through the openings to form a source region 5, drain region 6 for the P-channel insilated gate FET and a P type stopper or guard ring 22 (FIG. 2C). In this step, mask alignment is required with respect to the N type regions 3, 4 and 21.
It is assumed that as a result of a misalignment of the mask, the locations of the P type regions 5, 6 and 22 are displaced by + a in the direction X as shown in FIG. 1 with respect to the N type regions 3, 4 and 21.
Thereafter, the substrate 1 is again heated to form an insulating film thereon and then the insulating film is removed by photoetching where a gate electrode is to be formed. After that, the substrate 1 is heated to a high temperature to form thin gate oxide films 9 and 10 (FIG. 2D). In the above photoetching process, the mask alignment is carried out with respect to the N type regions 3, 4 and 21.
It is assumed that the gate oxide films 9 and 10 are displaced by - a in the X direction with respect to the N type regions 3, 4 and 21.
FIG. 2E shows the arrangement after the oxide layer has been partly etched away by photoetching to form openings 11, 12, 13 and 14. In this step, mask alignment is also necessary and let us assume that the openings 11, 12, 13 and 14 are displaced by - a in the X direction with respect to the N type regions 3, 4 and 21.
Then, a conductive material such as aluminum is evaporated on the entire surface of the substrate 1. After that the conductive material is etched away selectively by photoetching techniques to form a conductor 15 which connects the drains 4 and 6, a conductor 16 which connects the source 3 and a power source (not shown), a conductor 17 which connects the source 5 and a power source (not shown), a conductor 18 which connects gate electrodes 7 and 8, a conductor 19 which is connected to the conductor 18 and a conductor 20 which is connected to the conductor 15 to take out an output signal.
In the above described steps, mask alignment is also necessary relative to the N type regions 3, 4 and 21 and thus let us suppose the conductors 15, 16, 17, 18, 19 and 20 are also displaced by - a in the X direction.
In order to consider the relative displacements of the patterns and for convenience of explanation, the following suppositions will be made. The minimum required space between the drain region 6 and the stopper 22 is bp. The overlapping margin of the gate oxide film 10 and the drain region 6 or source region 5 is cp. The space margin between the drain region 6 and the opening 12 is dp. The overlapping margin of the gate electrode 8 and the drain region 6 or the source region 5 is ep. The overlapping margin of the stopper 22 and the elongated portion of the gate electrode 8 is fp. The depths of the source region 5 and the drain region 6 are X; and the expansion in the lateral direction of these is .alpha..xj. The distance between the drain 6 and the stopper 22 which is required from the standpoint of the operating characteristics of the element is h.
Under these assumptions, it is understood that the spaces or margins bp, cp, dp, ep or fp are required to satisfy the following equations: EQU bp .gtoreq. h + a + 2 .alpha. .sup.. Xj, EQU cp &gt; 2 . a - .alpha. .sup.. Xj EQU dp &gt; 2 . a - .alpha. .sup.. Xj EQU ef &gt; 2 . a - .alpha. .sup.. Xj EQU fp &gt; 2 . a - .alpha. .sup.. Xj.
Here, a is usually 1.5 .mu. to 3 .mu. and .alpha. . Xj is several tenths to seven tenths micron.
In FIG. 2F, bp is reduced by the amount of the sum of 2 .mu. . Xj, which represents the lateral expansion of the stoppers 21 and 22, and the displacement a which occured in the step shown in FIG. 2C. Thus the allowable minimum space becomes: EQU bp - (a + 2 .alpha. . Xj) = h.
With respect to cp, this is also reduced by the amount 2 a, which represents the displacement which occurred in the steps shown in FIGS. 2C and 2D. Therefore, the allowable limit of the margin cp becomes: EQU cp - (2 a + .alpha. . Xj) = 0.
With respect to dp, the allowable limit of this space margin becomes: EQU dp - (2 a + .alpha. . Xj) = 0
due to the displacement which occurred in the steps shown in FIGS. 2C and 2E. With respect to the ep, the allowable limit of this overlapping margin becomes: EQU ep - (2 a + .alpha. . Xj) = 0
due to the displacement which occurred in steps shown in FIGS. 2C and 2F.
Thus, in the conventional photoetching technique, the old pattern is used as a standard when a new pattern is formed and the relative displacement between the old and new patterns becomes extremely complex requiring further margins for spacing or alignment errors. For these reasons, there are limits to the miniaturization of patterns formed on substrates and the minimum overlapping or spacing margins between different patterns to permit adequate separation of the patterns. In manufacturing for integrated circuits, these limitations become especially troubling obstacles to minuturization of the circuits and cause decreasing yield rates.